The fabrication of integrated circuitry involves the formation of conductive lines over a substrate. Such conductive lines are used to connect to or with device components. One type of integrated circuitry is memory circuitry. Memory circuitry typically includes a memory array circuitry area in which storage devices are fabricated as close as lithography or other processing allows in order to conserve wafer space. Memory circuitry also typically includes peripheral circuitry in which the spacing requirements are not as paramount as in the memory array. Accordingly in many instances, devices in the peripheral circuitry area are typically spaced further apart relative to devices in the memory array circuitry area.
Transistor gate lines are commonly utilized in memory circuitry and peripheral circuitry. Such lines typically include sidewall spacers which electrically insulate the sides of the transistor gate lines. Such spacers are typically provided by forming a layer of insulative material over the substrate and anisotropically etching the layer to leave spacers about the sidewalls of the transistor gate lines.
The lateral width of spacers within memory arrays continues to get thinner as the distance between adjacent transistor gate lines reduces. Further in some instances, epitaxial semiconductive material, such as monocrystalline silicon, is grown from underlying substrate material as part of the source/drain regions of the transistors formed within the memory array area as well as in the peripheral circuitry area. Such growth is typically optimized for memory array circuitry performance, and requires process modification relative to the peripheral circuitry to achieve the desired operating circuitry in the peripheral circuitry array.
Further, reduction of spacer width within the memory array circuitry area undesirably results in increased parasitic capacitance between the spacers and transistor gates. This can adversely affect the speed and/or other performance characteristics of the individual transistors. Parasitic capacitance is increased or maximized by reducing the thickness of the dielectric between a pair of conductors and/or by increasing the dielectric constant “k” of the dielectric material between such conductors. It would be desirable to develop further methods which enable optimization of anisotropically etched spacer width over transistor gates lines within the memory array circuitry area differently or separately from the formation of such spacers within the peripheral circuitry area.
While the invention was motivated in addressing the above identified issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.